PMICs
Power Management of Integrated Circuits
With an increasing demand for computation and a rapid expansion of AI-based applications, traditional computing system architectures are reaching their limits. While systems have been designed based on data and bandwidth constraints for many years, their performance is now being hindered by power efficiency and the distribution of currents within the systems.
To illustrate this, Fig. 1.A and 1.B show respectively the GPU single precision FLOPS over time and the GPU Single Precision FLOPs/Watt. Although the number of operations continues to increase, improvements in performance per watt are progressing at a lower rate, leading to an increase in overall power consumption.
R. Prakash et al., “A 2400 W/in3 1.8 V Bus Converter Enabling Vertical Power Delivery for Next-Generation Processors,” 2024 IEEE Applied Power Electronics Conference and Exposition (APEC)
Digital power management strategies were initially focused on adjusting voltage supplies to meet targeted performance levels, utilizing various power modes and appropriate voltage and frequency scaling, with power converters located outside the package. However, with the increasing demands for high power and high clock frequencies, power converters need to be placed closer to the die load to minimize power paths impedance and voltage drops.
Achieving this integration at the nanometer scale presents significant challenges and is one of the primary objectives of the FAMES project.
PMIC stands for Power Management Integrated Circuit. The objective of the PMIC is to generate a regulated voltage supply to power an electronic system. Depending on the system specifications, the PMIC can be a linear regulator – offering better noise performance but lower power efficiency – or a switched converter – providing better power efficiency but suffering from voltage ripple. For high-performance computing systems, a key metric is the number of FLOPS per watt, and digital systems can tolerate voltage ripple. Therefore, switched DC-DC converters are typically preferred for digital systems.
In an ideal scenario, power converters would be monolithically integrated at the core of the computing system, using a single-stage step-down conversion to minimize currents and the resulting voltage drop due to parasitic resistance. However, since silicon technologies are not optimized in the same way for different applications (high voltages, high currents, and high frequencies are not compatible), complex systems have evolved in recent years toward heterogeneous chiplet integration. This approach allows for the management of different technological flavors within a compact 3D system.
This evolution paves the way for a separate PMIC component that is deeply integrated into the system through a chiplet topology. With PMICs being part of the chiplet integration, it minimizes board-level power components and overall system size, enables more granular power management strategies, and shortens power paths.
Switched converters consist of power switches, whose on-resistance should be minimized, and passives that serve as energy storage elements, primarily capacitors and inductors. Despite advancements in high-frequency power converter architectures, which allow for smaller passive components, the monolithic integration of power passives with CMOS technology remains insufficient to meet the anticipated power densities.
In FAMES, we will focus on system-to-components co-optimization to work on the integration of passive components in a dense 3D topology, considering interconnect possibilities and their impact on performance.
Two types of PMICs will be addressed in the FAMES project: capacitive DC-DC converters relying on high-density capacitors, and inductor-based DC-DC converters.
The second objective will be pursued through collaboration with Tyndall, which explores the dense integration of power magnetics-on-silicon to create miniaturized inductors and develops new interconnection processes such as micro-transfer printing (see figure below) of power passives.
Figure 1 – Tyndall magnetics-on-silicon components
Figure 2 – Full wafer magnetics-on-silicon, Tyndall
This will enable European companies to build their global competitiveness in Power Supply in Package (PSiP), Power Supply on Chip (PwrSoC), and ultimately, to develop leadership in the area of granular power management on the FD-SOI platform.
Figure 3- Micro Transfer Printing: Process Flow for Micro Inductors on Silicon
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