The upcoming Design School at Cime-Nanotech in Grenoble, scheduled from January 25 to 30, will be the first in a series of annual schools running from 2026 to 2028.

Semiconductor designers face significant scientific and industrial challenges, including balancing power, performance, and functionality in modern analog, RF, and digital circuits. FD-SOI technology offers unique advantages, such as body-biasing techniques and advanced transistor features, which can improve performance, reduce power consumption, and provide design flexibility.

By sharing the latest practices and knowledge, the school will help participants understand how to leverage FD-SOI to develop more efficient and innovative semiconductor solutions. Participants will have the opportunity to explore the full FD-SOI design flow, from transistor modeling and characterization to analog/RF circuit design and digital design as well as a presentation on the design kit.

Sunday, Jan 25th 2026:

• Welcome and introduction to the Winter School
• Presentation of three basic FD-SOI models

Monday, Jan 26th 2026:

• Physical principles of compact models
• Design rules in FD-SOI 28nm

Tuesday, Jan 27th 2026:

• Digital functionalities of FD-SOI 28nm IC
  • Design flow overview (from RTL to layout)
    • Sign-off RTL
    • Middle-end with constrained synthesis
    • Back-end (floorplanning, clock tree, body bias, routing, sign-off layout, …)
  • Hands-on training on digital circuit example

Wednesday, Jan 28th 2026:

• Novel embedded non-volatile memories for FD-SOI 28nm and advanced FD-SOI nodes
• Immersive tour of the CEA-Leti clean room
• Evening Social Event

Thursday, Jan 29th 2026:

• ACM model for FDSOI
• gm/Id methodology
• Parameter extraction
• Practical training on RF circuit design (LNA)

Friday, Jan 30th 2026:

• FD-SOI low power aspects
• Wrap up

The planned Design School represents a critical step for the FAMES project by demonstrating the practical advantages of FD-SOI technology for both analog/RF and digital circuits. It also validates the teaching and research approach of the project, showing that designers can efficiently apply body-biasing and advanced modeling techniques to real-world circuits, thereby accelerating the adoption of FD-SOI in next-generation semiconductor applications.