Private Area

Logo FAMES header

OPEN-ACCESS

FAMES Pilot Line

The FAMES Pilot Line offers European semiconductor stakeholders from industry, research, and academia access to a unique slate of advanced semiconductor technologies, chip design, testing, demonstrators and manufacturing capabilities.

This initiative aligns with the EU Chips Act to bolster the EU’s semiconductor industry and support European technological sovereignty. Collaboration with other pilot lines in Europe will help build a tightly interconnected European chip ecosystem.

Access FAMES pilot Line technologies
© P.JAYET / CEA

FAMES technologies

Access to the FAMES Pilot Line technologies is now Open!

Join the FAMES community and be part of tomorrow’s resilient European chip industry!

The FAMES Pilot Line provides chipmakers, startups, fabless companies and academics with a pathway to high-performance, low-power chips.

Access and explore:

  • Advanced FD-SOI technologies,
  • Embedded non-volatile memories,
  • 3D integration options,
  • RF switches, filters, capacitors and circulators,
  • Power management integrated circuit solutions.

Create new growth opportunities for your organization and reinforce Europe’s industrial leadership.

The wide array of FAMES technologies is available by:

Open Access Call Button - FAMES Pilot Line
  • Annual Open-Access Call
Spontaneous Request Button - FAMES Pilot Line
  • Spontaneous user request

Annual Open-Access Call N°1

Opening: March 18th 2025

Closing: May 16th 2025 at 23h59 CET (deadline for submissions)

The 2025 annual call is closed.
The 2026 Open-Access Call will be launched on March 9, 2026. Please consult our website again mid-January for more details

If you are interested in FAMES’ advanced technologies, please submit a Spontaneous User Request.

Open Access Call Process - FAMES Pilot Line

Technologies

Evaluate the remarkable benefits of FD-SOI advanced nodes and BEOL eNVM:
performance, size, design flexibility (body-biasing option), low power consumption

Pathfinding PDKs

Access unique memory advanced demonstrator multi-project wafers (MAD MPW) and
test the advantages of FeRAM embedded in the Back End of Line (BEOL)

PDKs giving access to Silicon MPW

3D stacking technologies enhance functionalities, improve performance and optimize cost:
combine different chips and dies for your specific application using TSVs and copper pads

3D Heterogeneous Integration options

Upcoming Workshops

To get explanations directly from the project coordinator, join our Upcoming Workshops.

Spontaneous User Request

The FAMES Pilot Line is currently accepting Spontaneous User Requests, if your needs go beyond the 2025 Open-Access Call.

Once you submit a Spontaneous User Request to access the FAMES Pilot Line,

The Open Access Committee (OAC) will evaluate its eligibility and, if it is eligible, appoint a Lead Partner to your request.

The Lead Partner will:

  • Contact you for a first exchange, to clearly understand your needs. An NDA may be signed at this time for this purpose.
  • Co-construct an R&D User Project with you, corresponding to your needs.

The use of the Pilot Line is subject to fair, reasonable and non-discriminatory terms and conditions.

All access requests submitted by Potential Users will be evaluated for eligibility, technical feasibility and pilot line capacity uptake.

In the event that too many eligible requests are received compared to the capacity of the line, ranking criteria will be used to prioritize the different User Requests. The eligibility and ranking criteria are listed in the dedicated section of the User Guidelines and Procedures document.

For more details, please refer to the User Guidelines and Procedures.

Submit a request

User Guidelines and Procedures

User Guidelines and Procedures – full text

 

Technological portfolio

User Access Governance

User Request Selection and Ranking Criteria

Pricing and Estimated Leadtimes

Multi-partner projects

IP and Know-How

Statistical tracking of User Projects

Personal Data Protection

Submission forms content

Confidentiality

User Access Contact

Download the guidelines

Frequently Asked Questions

Eligibility refers to the regulations of the European Commission and the participating States concerning the contribution of companies and research institutions to the European semiconductor ecosystem. The Eligibility criteria are listed in Section 5 of the User Guidelines and Procedures.

Please consult the FAMES User Request timeline.

FAMES Open Access Call - Process Timeline

In the event of a User Request overflow, some User Requests will be put on a waiting list. Two months after the submission deadline of the FAMES-Open-Access Call, the waiting list will be reviewed by the Open Access Committee and new User Requests may be selected if the Pilot Line capacity allows it. At this point, Users will be notified of the status of their Request. If their Request cannot be accepted this time around, and depending on the technology requested, it may be possible to resubmit a Request during the following FAMES-Open-Access Call, in 2026.

FAMES Open-Access Calls will take place every year from 2025 to 2028. They will open in March and close in May.

PDKs are accessible for free but require signing an NDA and a Design Kit License Agreement (DKLA).

The price/mm2 of the FAMES MPWs will depend on each User’s specific (new) design and will therefore be calculated and communicated to each User on a case by case basis.

The Open Access Chairperson will be glad to answer any questions you may have regarding the submission form and the FAMES technologies.

Logo FAMES footer
  • Plan de site
  • Mentions légales

Website designed and made by Perceptiom and FAMES

FAMES is a European Union’s Horizon Europe Research and Innovation programme

Website designed and made by Perceptiom and FAMES

Logo FAMES footer
The FAMES Pilot Line of the Chips JU is funded by Horizon Europe and Digital Europe Programs and  the National Public Authorities of the partners involved.
Grants N° 101182279 and 101182297.

Website designed and made by Perceptiom and FAMES

Spontaneous User Request

Please note that your answers will help us establish the eligibility of your request.

All FAMES Partners undertake to respect their obligations in application of regulations in force and, especially, regulation (EU) 2016/679 of the European Parliament and of the Council of 27 April 2016, on the protection of natural persons with regard to the processing of personal data and on the free movement of such data (referred to as “GDPR”).

FD-SOI 10nm Pathfinding PDK

Pathfinding PDK - FD-SOI technologies - FAMES Pilot Line
Credit: CEA-Leti – SEMulator3D ®

10nm FD-SOI Pathfinding PDK – release 1 (digital circuits)

Expected timeline:

  • Release 1 will be available end of 2025.

    Release 2, which will have analog and RF options too, will be available Q1 2027.

Overview

FAMES offers a Pathfinding PDK to evaluate the performance of the 10nm FD-SOI CMOS technology. Based on process and device TCAD simulations and silicon data, this first release allows for assessment of digital circuits. Process assumptions are based on the most recent generations of FD-SOI technology enabling 68nm CPP and 48nm metal pitches. It contains logic standard cell libraries with multi-Vt flavors, SPICE models, tools for physical verification, and a parasitic extraction tool for post-layout simulations.

Based on virtual advanced FD-SOI technologies, this PDK will allow users to create new design architectures that benefit from Body bias compensation, mechanical stress engineering for both NMOS and PMOS devices, and new routing solutions, among others.

Access and technical support

Accessing the Pathfinding PDK is free of charge but Users must sign an NDA and a Design Kit License Agreement (DKLA) before gaining access to the PDK.

FAMES Pathfinding PDK users will have access to technical support from FAMES experts and the possibility of building and publishing model case studies with one or more FAMES partners.

PDK Specifications and Contents

  • Design Rule Manual
  • Device library including multi-Vt MOSFET for schematics and layouts
  • Device model library supporting multi-Vt solutions for SPICE simulation
  • Process variability and corner support
  • DRC/LVC deck files for physical verifications
  • PEX extraction tool
  • Digital standard cell libraries (100+ cells)
  • SRAM bitcells

Enabling tools required

  • Design/Layout: Virtuoso® Layout Suite (Cadence)
  • Electrical Simulation: Xpedition AMS (Siemens EDA) and HSPICE® (Synopsys)
  • Physical Verification (DRC/LVS):  Calibre® (Siemens EDA)
  • Parasitic Extraction (PEX): StarRC® (Synopsys)
  • Place and Route: Innovus® (Cadence)

Process Design Kits (PDKs) giving access to Silicon

Access PDKs giving access to Silicon- Technologies - FAMES Pilot line
Credit: CEA-Leti/S. Martin et al, “Hf0.5Zr0.5O2 FeRAM scalability demonstration at 22nm FDSOI node for embedded applications”, IEDM Symposium 2024

PDK add-on to access a Memory Advanced Demonstrator (MAD)

Expected timeline 

Design your specific FD-SOI + embedded FeRAM circuit in time to meet the design freeze planned for end 2025.

Overview

FAMES offers a 300mm technology platform dedicated to embedded Non Volatile Memories (eNVM). This technological option can be added to semiconductor foundry CMOS technologies. The result is one or more specific eNVM memory devices located within the Back-End-of-Line (BEOL).

FAMES is developing eNVM technologies in various « flavors ». Each eNVM flavor offers key features that address specific application requirements. An embedded Ferroelectric Random Access Memory (FeRAM) PDK add-on is currently available.

Embedded FeRAM is one of the FAMES technologies available in 2025. It is a high reliability, high-speed, low power memory device perfectly adapted for energy-efficient systems, that could advantageously replace conventional eFlash memories.

Access and technical support

Accessing the FAMES PDK add-on for embedded FeRAM is free of charge but Users must sign an NDA and a Design Kit License Agreement (DKLA) before gaining access to the PDK.

NB: Having previously secured access to GlobalFoundries’ 22FDX PDK is a pre-requisite to using the FAMES PDK add-on.

FAMES PDK add-on users will have access to technical support from FAMES experts.

PDK Specifications and Contents

  • Design Rule Manual – Fully compatible with GF’s 22FDX core technology PDK
  • Device library including NVM bitcells for schematics and layouts
  • Device model for SPICE simulation
  • Process variability and corner support
  • DRC/LVC deck files for physical verifications

 

Technological features

  • 300 mm CMOS core technology: 22nm FD-SOI
  • 10 Metal layers

Enabling tools required

  • Analog design & layout: Virtuoso® Layout Suite (Cadence)
  • Electrical verification: Spectre® (Cadence) and PrimeSim™ XA simulator (Synopsys)
  • Physical verification (DRC/LVS): Calibre® (Siemens EDA SW)

 

Other related R&D Services

  •  Design-for-test expertise
  • Circuit testing
  • eNVM expertise to analyse test results

 

If you would like to obtain any of these additional services, please mention it on the User Request submission form in the comments area.

3D Heterogeneous Integration options

Access 3D Heterogeneous Integration options - FAMES Pilot line
© R.Franiatte/CEA
Access 3D Heterogeneous Integration options - FAMES Pilot line
© L.Sanchez/CEA

3D Heterogeneous Integration options

Overview

FAMES 3D heterogeneous integration solutions will make new IC architectures possible by enabling die to wafer assemblies and 3D chiplet designs. Such architectures will benefit from higher density, speed and endurance, and lower power consumption, an excellent trade-off for many applications, such as automotive, AI at the edge, and high power computing. CEA-Leti has an outstanding track record in this field and an aggressive and forward-looking roadmap in this domain.

The use of interposers for interconnect routing in 3D IC architectures currently limits compactness, with at best 20 to 30 micron pitches of micro-bumps for vertical connections. The FAMES 3D heterogeneous integration technology platform opens up the possibility for superior integration of functions exhibiting higher signal integrity and lower latency in the bottom die (including power distribution and memory), much denser vertical interconnects (based on direct hybrid bonding), and shorter and more closely packed interconnects (x50-x100 versus the current copper pillar baseline). In this way, FAMES 3D interconnects increase chip-to-chip bandwidth and limit overall power consumption.

The FAMES technological modules and specifications currently available are described in Table 1.

Available now

Let’s build together the best 3D solution for you!

Coming soon

Accessing the technology

Users may obtain access to the FAMES 3D Heterogeneous Integration Design Rule Manual (DRM) by signing an NDA and a Design Kit License Agreement (DKLA).

FAMES DRM users will have access to technical support from FAMES experts.

Contact

Open Access chair person - FAMES Pilot Line

Open Access Chairperson

Susana Bonnetier (CEA-Leti)

For inquiries or problems regarding the Open Access/Spontaneous Request, you can contact us directly.

Subscribe to the newsletter

Keep up to date with the latest news from FAMES

All FAMES Partners undertake to respect their obligations in application of regulations in force and, especially, regulation (EU) 2016/679 of the European Parliament and of the Council of 27 April 2016, on the protection of natural persons with regard to the processing of personal data and on the free movement of such data (referred to as “GDPR”).

Contact

Leader of Work Package ​​3D and heterogeneous integration

Lilian Masarotto (CEA-Leti), Senior project manager

Request submitted!

Understood!

Thank you for your registration. You will receive a copy by email. We will be getting in touch with you shortly to confirm or not your registration to the Winter school.

If you encountered an error or did not receive a copy (please check your spam), contact us.

FAMES European FD-SOI Design School (EFDS)

Winter School – 25-30 January 2026, Grenoble,  France
training costs: 1960€

All FAMES Partners undertake to respect their obligations in application of regulations in force and, especially, regulation (EU) 2016/679 of the European Parliament and of the Council of 27 April 2016, on the protection of natural persons with regard to the processing of personal data and on the free movement of such data (referred to as “GDPR”).

Spontaneous User Request

Please note that your answers will help us establish the eligibility of your request.

If you selected "3D Heterogeneous Integration Process Modules", please provide more details, otherwise please proceed to the next step.

All FAMES Partners undertake to respect their obligations in application of regulations in force and, especially, regulation (EU) 2016/679 of the European Parliament and of the Council of 27 April 2016, on the protection of natural persons with regard to the processing of personal data and on the free movement of such data (referred to as “GDPR”).

Request submitted!

Thank you for your request. You will receive a copy by email. We will be getting in touch with you shortly.

If you encountered an error or did not receive a copy (please check your spam), contact us at open-access-chair@fames-pilot-line.eu.

Understood!

FAMES Open-Access Call User Request

Please note that your answers will help us establish the eligibility of your request.

All FAMES Partners undertake to respect their obligations in application of regulations in force and, especially, regulation (EU) 2016/679 of the European Parliament and of the Council of 27 April 2016, on the protection of natural persons with regard to the processing of personal data and on the free movement of such data (referred to as “GDPR”).

Trainings

CV :

Annual call