NEWS & RESULTS

Articles in Journal

Tran, N. P., Tran, N., Milesi, F., Le, V. H., Zouknak, L. D., Dezest, P., … & Fenouillet-Beranger, C. Toward Full Relaxation of Ssoi Substrates for Pfet Device Fabrication. P. and Rodriguez, Philippe and Brunet, Laurent and Duriez, B. and Cyrille, MC. and Fenouillet-Beranger, C., Toward Full Relaxation of Ssoi Substrates for Pfet Device Fabrication. doi: 10.1016/j.sse.2025.109196

Zouknak, L. M., Le, V. H., Tran, N. P., Milesi, F., Hartmann, J. M., Jarjayes, S., … & Fenouillet-Beranger, C. (2025). Nanoscale SOI strain engineering: STRASS-enabled local stress optimization. Solid-State Electronics, 109215. doi: 10.1016/j.sse.2025.109215

Martínez, A., Márquez, C., Lorenzo, F., Gutiérrez, F., Caño-García, M., Ávila, J., … & Gámiz, F. (2025). Wafer-Scale Demonstration of BEOL-Compatible Ambipolar MoS2 Devices Enabled by Plasma-Enhanced Atomic Layer Deposition. ACS Applied Materials & Interfaces. https://pubs.acs.org/doi/10.1021/acsami.5c12014

Bazzi, A., Levices, H., Talatchian, P., Badets, F., & Hutin, L. (2025). Ising-inspired invertible adders using coupled phase-locked CMOS ring oscillators. Physical Review Applied, 24(1), 014004. doi: https://doi.org/10.1103/8xc2-vkk3

Fenouillet-Beranger, C., Rozeau, O., Chouk, R., Cueto, O., Royet, A. S., Charbonneau, M., … & Noguet, D. Pursuing the Fd-Soi Roadmap Down to 10-7nm Nodes for High Energy Efficient, Low Power and Rf/Mmwave Applications. doi: 10.2139/ssrn.5316840

Barge, D., Gallard, M., Hartmann, J. M., Fournel, F., Loup, V., Mazen, F., … & Servant, F. 300 Mm Ssoi Engineering with Ultra Thin Box. Available at SSRN 5316841: doi.org/10.2139/ssrn.5316841

Marquez, C., Gity, F., Galdon, J. C., Martinez, A., Salazar, N., Ansari, L., … & Gamiz, F. (2025). On the Enhanced p‐Type Performance of Back‐Gated WS2 Devices. Advanced Electronic Materials, 2500079. doi: https://doi.org/10.1002/aelm.202500079

Lèquepeys, JR., Noguet, D., Paing, B. et al. Europe’s pilot line on fully depleted silicon-on-insulator technology (FAMES). Nat Rev Electr Eng 2, 77–78 (2025). https://doi.org/10.1038/s44287-025-00144-y

Milesi, F., Rodriguez, P., Zouknakl, L.D.M. et al. Process challenges of the STRASS technique to increase the electron mobility in advanced FD-SOI nMOSFETs. MRS Advances 10, 174–178 (2025). https://doi.org/10.1557/s43580-025-01148-4

Publications in Conference proceeding/workshop

Persson, K. M., Eskelinen, P., Kaatranen, O., & Kilpi, O. P. (2025, June). ITO Contact Optimization for Enhancement Mode BEOL MOSFETs. In 2025 Device Research Conference (DRC) (pp. i-ii). IEEE.

C. Fenouillet-Beranger et al., Ultra-Thin-Body and Buried Oxide FD-SOI next generation nodes and eNVM technologies for advanced IC design, 2025 IEEE 28th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), Lyon, France, 2025, pp. 105-114. doi: 10.1109/DDECS63720.2025.11006678

Publications in Conference proceeding/workshop

Lespiaux, J., Kanyandekwe, J., Marion, T., Saidi, L., Lapras, V., Bond, A., … & Hartmann, J. M. (2024). Selective Epitaxial Growth of SiGe (: B) for Advanced p-Type Fd-SOI. ECS Transactions, 114(2), 271. doi: 10.1149/11402.0271ecst

Kanyandekwe, J., Hartmann, J. M., Lespiaux, J., Marion, T., Saidi, L., Lapras, V., … & Glorieux, O. (2024). Selective Epitaxy of Tensile, Highly Doped SiP for Planar NMOS FD-SOI Devices. ECS Transactions, 114(2), 253. doi: 10.1149/11402.0253ecst

A. -S. Royet et al., Calibration Insights of Phosphorus Diffusion Model for NMOS FDSOI : Pathway to Advanced Technology Nodes, 2024 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), San Jose, CA, USA, 2024, pp. 1-4, doi: 10.1109/SISPAD62626.2024.10733008.

Rodriguez-Fano, M., Pedini, J. M., Cadot, S., Grampeix, H., Magis, T., Laulagnet, F., … & Barraud, S. (2024, September). Comparative study of ALD MoS 2 on high-k dielectrics for the fabrication of nanowire FETs. In 2024 IEEE European Solid-State Electronics Research Conference (ESSERC) (pp. 129-132). IEEE. doi: 10.1149/11402.0271ecst

Boujnah, A., Cueto, O., Jaud, M. A., Martinie, S., Nallet, F., Fenouillet-Beranger, C., & Rozeau, O. (2024, September). DTCO of advanced FDSOI CMOS technology by process emulation. In 2024 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) (pp. 01-04). IEEE. doi: 10.1109/SISPAD62626.2024.10733323

Royet, A. S., Chouk, R., Cueto, O., Kanyandekwe, J., Lapras, V., Jaud, M. A., … & Rozeau, O. (2024, September). Calibration Insights of Phosphorus Diffusion Model for NMOS FDSOI: Pathway to Advanced Technology Nodes. In 2024 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) (pp. 1-4). IEEE. doi: 10.1109/SISPAD62626.2024.10733008

D. Bosch et al., Breakthrough Processes for Si CMOS Devices with BEOL Compatibility for 3D Sequential Integrated more than Moore Analog Applications, 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Honolulu, HI, USA, 2024, pp. 1-2, doi: 10.1109/VLSITechnologyandCir46783.2024.10631398.

Jarjayes, S., Brunet, L., & Rodriguez, P. (2024, April). Analysis of the key parameters of box creep process for advanced FDSOI devices. In 2024 25th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE) (pp. 1-4). IEEE. doi: 10.1109/EuroSimE60745.2024.10491442

J. Lugo-Alvarez et al., First Radio-Frequency Circuits Fabricated in Top-Tier of a Full 3D Sequential Integration Process at mmW for 5G Applications, 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Honolulu, HI, USA, 2024, pp. 1-2, doi: 10.1109/VLSITechnologyandCir46783.2024.10631483.