High-Bandwidth CMOS regulated cascode based transimpedance amplifier for short-range Optical communication

Designed in a 22 nm FD-SOI technology and operating from a 0.8 V supply, the Regulated Cascode (RGC) based TransImpedance Amplifier (TIA) achieves a transimpedance gain of 75.5 dBΩ and a −3 dB bandwidth of 4.3 GHz while driving a 150 fF GaN photodiode. The circuit consumes only 170 μW confirming its suitability for energy-efficient micro-optical interconnects and parallel chip-to-chip communication systems. Large-signal simulations demonstrate reliable operation at 6 Gb/s.

The increasing demand for short-range optical interconnects in data-center and chiplet-based systems is driven by stringent requirements on bandwidth, latency, signal integrity, and energy efficiency. Parallel optical links have emerged as a promising solution to supporting multi-Gb/s data rates per channel and to address the limitations of electrical interconnects, in line with evolving standards such as the Universal Chiplet Interconnect express (UCIe).

In this context, GaN-on-Si micro-LED and micro-photodiode optical links are emerging as a promising solution for dense chiplet integration, where the performance of the transimpedance amplifier directly determines the achievable bandwidth, sensitivity, noise performance, and overall system stability. While massive parallel communication enables simple modulation scheme (Non-Return to Zero – NRZ) it implies reduced silicon area, reduced power consumption and high-power supply rejection ratio due to matrix integration.

Various TIA topologies have been reported, including active-feedback, resistive-feedback architectures and RGC-based topologies. But most of them struggle to fulfill all previous mention requirements. Thanks to the intrinsic 22FDX technology performance and accurate theorical study, a differential RGC based TIA has been designed achieving a transimpedance gain of 75.5 dBΩ and a −3 dB bandwidth of 4.3 GHz while driving a 150 fF GaN photodiode. Its input referred noise current integrated over the bandwidth is only 637 nA. The circuit consumes only 170 μW. Fig. 1 and Fig. 2 show the simulated transimpedance gain and input noise current spectral density respectively. Large signal transient simulation using 6 Gbps Pseudo-Random Binary Sequence (PRBS) source shows a wide-open eye diagram (Fig. 3).

The circuit has been layouted, the TIA core surface is only 16µm x 22µm. tapeouted in August 2026, under probe measurement are expected by Q1 2027. The circuit has been implemented in a complete optical receiver including limiting amplifier, offset control feedback loop and decision circuit to enable 2D wire bonding measurement with GaN photodiode.

Additional links or documents

“High-Bandwidth CMOS Regulated Cascode TIA for Short-Range Optical Links”
Aicha Amou, Frédéric Hameau, Gilles Sicard, Bertrand Gomez, IEEE NEWCAS 2026 conference