For decades hardware security has been shaped by the security component market—such as ID and banking—and by the demands of Common Criteria or EMVCO standards. However, in our increasingly interconnected world, cyber risk has become a significant concern, necessitating trusted systems at the hardware level. This shift has spurred various initiatives, like the Cyber Resilience Act, and new standards, such as SESIP and ISO21434, which impose stricter requirements on components and their potential vulnerabilities.

These challenges need to be considered within an industrial landscape where CMOS bulk technologies face competition from FD-SOI and FinFET. IC suppliers must make critical decisions, keeping hardware security requirements as a priority

It is then essential to examine the potential and inherent strengths of silicon technologies. FD-SOI offers intrinsic advantages due to its engineered substrate, which allows for channel isolation from the substrate, where the most dangerous attacks, such as ‘Laser Fault Injection,’ originate. However, there have been few experiments conducted on FD-SOI, and its specific physical mechanisms remain unmodeled.

CEA-Leti and SOITEC have published at IOLTS 2026 conference an article entitled “FD-SOI rather than Bulk – Further experimental investigation of laser induced fault mechanisms in FD-SOI” that is highlighting breakthrough results on security characterization of FD-SOI when facing laser. The sensitivity of the FD-SOI technology is shown as:

• 5 times less sensitive in vertical dimension
• 30 less sensitive in lateral dimension

Practically this makes the detection of a first fault about 60 times longer on FD-SOI than on bulk.

This first characterization of the technology’s behaviour under laser attacks represents the first step towards the development of a physical fault model. This model will subsequently enable the design of intrinsically laser-resistant logic gates on FD-SOI, paving the way for more robust systems.

This study positions FD-SOI as a critical CMOS security technology for mitigating perturbation attacks—attacks so severe that they can corrupt program execution, disable countermeasures, or compromise cryptographic implementations at the hardware level.

SOITEC has been a key partner in this project. SOITEC is already interested in another outcome of the FAMES project. It consists in the proposition to develop a cyber-resilient substrate that would bring a definitive protection to any IR illumination in backside to any digital products on FD-SOI.

Finally, the FAMES project aims at making the silicon technologies of our tomorrow’s digital systems intrinsically more secure and then fulfilling the ambition of the CRA and the Chips Act.