A step forward in the maturity of 3D Sequential Integration (3DSI), where 5G (30GHz) RF circuits are stacked directly above a running digital circuit is demonstrated. It was shown that vertical digital/RF co-integration exhibits cross-talk only in specific conditions which may be properly handled by design and frequency plan definition despite the ultra-short proximity between tiers specific to 3DSI.
The 3D Sequential Integration (3DSI) process delivers the highest 3D contact density for “More Moore” and “More than Moore” applications. It uniquely enables the co-integration of digital and RF circuits across multiple levels, reducing total parasitics through shorter interconnection lengths. Two key questions remain at this stage:
Within the FAMES project framework, this device and circuit analysis have been conducted. The work addresses the aforementioned challenges. For the first time, Radio Frequency Integrated Circuits (RFICs) have been stacked at the top tier of a 3D sequential integration. The analog silicon RF circuits, sequentially fabricated at 500°C above a digital circuit layer using a 28nm FDSOI industrial platform, are functional.
The device performance (Ft = 123 GHz, Fmax = 178 GHz) is high enough to demonstrate top-tier voltage-controlled oscillator (VCO) and low-noise amplifier (LNA) functional demonstrators in the 30 GHz band. Additionally, a signal integrity study has been conducted using a ring oscillator aggressor integrated on the bottom tier below the VCO core, highlighting the interoperability of aggressive vertical co-integration between fast digital and RF blocks.
This work provides insights into potential crosstalk issues arising from the ultra-short distance between tiers, a distinctive feature of 3DSI. The conclusion is that RF crosstalk can be effectively managed through design and frequency plan definition
Perrine Batude, CEA-Leti
Luge-Alvarez, J., David, J. B., Siligaris, A., Puyal, V., Moritz, G., Mota-Frutuoso, T., … & Batude, P. (2024, June). First Radio-Frequency Circuits fabricated in top-tier of a full 3D Sequential Integration Process at mmW for 5G applications. In 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) (pp. 1-2). IEEE.
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