FAMES European FD-SOI Design School (EFDS)

Objectives

Analog and RF designs can take advantage of FD-SOI by using body-biasing techniques and advanced features. Indeed, the best and specific practices in analogue design helps the FDSOI technology to set us apart. Similarly, designing digital circuits in FD-SOI is technically demanding because of the power/performance trade-off, which is managed thanks to the body-bias control. This implies to be aware of the complete design flow covering high-end simulations as well as back-end features. The aim is to provide designers with the foundations they need to develop chips using the FD-SOI technology.

Audience

Any designer working in the field of circuit design (Master, Engineers, PhDs) keen to understand the circuit design developed in the framework of the FAMES Pilot Line.

Prerequisites

This course will be designed for chip designers. The objective is to provide a scientific and technical approach of the FD-SOI chip design flow

Syllabus of courses and hands-on trainings

Transistor modelling

• FDSOI transistor modelling (parasitic effects, coupling effects, …)
• IV characterization with FD-SOI (coupling effect)

Analog and RF design

• ACM2 and EKV model for FD-SOI
• Gm/Id model and circuit design
• Parameter extraction
• RF circuit design (LNA)
• Practical trainings

Digital circuit design

• FD-SOI digital design flow (from RTL to layout)
• Sign-off RTL
• Voltage, Power and Body bias domain definitions (UPF)
• Middle-end with constrained synthesis
• Static timing analysis
• Back-end (floorplanning, clock tree, body bias, routing, sign-off layout, …)
• Practical trainings

Design for Test

• Digital test (Fault models, ATPG, DfT, Memory test, …)
• Test techniques for mixed and analogue circuits
• RF test
• Practical trainings