Combinatorial optimisation is used logistics, scheduling, chip design and resource allocation, yet the number of possible solutions increases rapidly as problems grow. Conventional processors repeatedly transfer data between memory and computing units, adding both latency and energy costs. Hardware Ising machines offer an alternative by mapping optimisation problems onto interacting binary variables that naturally evolve towards low-energy solutions.

The team brought together two complementary nanotechnologies in a single computing loop. Hafnium-oxide RRAM devices store programmable, multilevel couplings and perform analogue multiply-and-accumulate operations, while stochastic magnetic tunnel junctions (sMTJs) act as thermally fluctuating probabilistic bits. Increasing the RRAM read voltage strengthens the coupling signal while progressively reducing spin randomness, providing an intrinsic annealing mechanism with minimal additional control circuitry.

Operating at room temperature and without an external magnetic field, the prototype consistently reached the global optimum for a 24-vertex weighted MAX-CUT problem and a 10-vertex, three-colour graph-colouring problem. The study also demonstrated that the programmed RRAM states remained stable over one month and that CMOS-integrated sMTJs are suitable for fast probabilistic computing.

FAMES supported the device-fabrication activities and energy-modelling work by funding the research manpower required to carry them out. This support helped the team advance from an experimental proof of concept towards a broader assessment of the architecture, including its energy efficiency and potential for future integration.

The result provides a concrete application for the emerging-memory and low-power-computing technologies developed within the FAMES pilot line. By demonstrating that RRAM devices and sMTJ can operate together in a functional optimisation accelerator, the work establishes the feasibility of combining these technologies in future integrated systems.

The architecture is designed to reduce energy per computation by limiting data movement between memory and processing units. Because the problem parameters are stored directly in the RRAM array, key operations are performed close to the data, addressing one of the main sources of energy consumption in conventional computing architectures.

Potential applications include transport routing, industrial scheduling, power-grid management, chip design, embedded AI and scientific computing. The hardware supports both Ising (−1/+1) and quadratic unconstrained binary optimisation (QUBO, 0/1) formulations, allowing a broad range of optimisation problems to be addressed on the same platform.

Further development of this concept would require closer integration of the RRAM arrays, sMTJs and control electronics, potentially using 2.5D, hybrid-bonded or monolithic 3D approaches. Other possible directions include parallel updates using multiple sMTJs, demonstrations on larger problems, improved tolerance to device variability, and systematic comparisons of time-to-solution and energy consumption with conventional processors.