Relaxation of sSOI substrate for 10nm nMOS and pMOS FD-SOI devices co-integration

Introduction of strain is one of the main levers in order to achieve the performance for the new generation of 10nm FD-SOI devices. Tensile stress enhances the electron mobility for nMOS and hole mobility is improved by compressive stress for pMOS. In the case of sSOI (strain SOI) wafers, relaxing the tensile silicon for pMOS appears to be beneficial to facilitate the Ge condensation process (i.e., compressive strain). FAMES’ work published at the last EUROSOI-ULIS conference in April 2025, demonstrates 85% relaxation of a 1.25 GPa tensile sSOI wafer. Multiple iterations of ion implantation and annealing are also a promising solution and may be a path for further relaxation, making sSOI substrate essential for FD-SOI scaling.
Schema relaxation sSOI
CEA-Leti

Introduction of strain is one of the main levers in order to achieve the performance for the new generation of 10nm FD-SOI devices. Tensile stress enhances the electron mobility for nMOS and hole mobility is improved by compressive stress for pMOS. In the case of sSOI (strain SOI) wafers, relaxing the tensile silicon for pMOS appears to be beneficial to facilitate the Ge condensation process (i.e., compressive strain). FAMES’ work published at the last EUROSOI-ULIS conference in April 2025, demonstrates 85% relaxation of a 1.25 GPa tensile sSOI wafer. Multiple iterations of ion implantation and annealing are also a promising solution and may be a path for further relaxation, making sSOI substrate essential for FD-SOI scaling. 

Scaling down the FD-SOI transistor size alone does not bring sufficient benefits to meet the performance roadmap. In the FAMES project, performance “boosters” are being researched and implemented to build FD-SOI next nodes.

One of the key boosters for 10 nm FD-consists in increasing the carrier mobility in the channel. The use of intrinsically strained channels is very effective to enhance carrier mobility.

Unfortunately, the strain required to increase nMOS and pMOS differ: tensile strained silicon is required for nMOS whereas compressive strained via SiGe channel for pMOS. The tensile layer (~+1.4 GPa) can be obtained at the wafer scale via sSOI strained SOI.

Such substrates show +33% Ieff gain as compared to conventional SOI substrates for nMOS devices. On the other hand, compressively strained-SiGe channel obtained by the Ge enrichment technique is interesting for pMOS devices.

However, in order to compensate or generate a 20% to 30% Ge condensed channel in sSOI wafer, a ratio of Ge around 50% epitaxy is required. A high Ge% could be difficult to integrate in devices (issues regarding threshold voltage adjustment).

To avoid this issue, it is preferable to relax the tensile stress of sSOI wafers before the condensation process. In the FAMES project, we have shown that by amorphizing the Si film on sSOI wafers by Si or Ar ion implantation, followed by annealing results in the relaxation of the tensile stress.

To enter further into the details, 3 implantation conditions (Si1, Si2 and Ar) have been tested. The goal of ion implantation is to amorphize a substantial portion of the thin sSi film while leaving enough crystalline regions on top to facilitate stress relaxation and subsequent recrystallization. All implanted wafers were then annealed at 850 °C for 5 minutes in a furnace to allow recrystallization down to the BOX.

This has been successfully demonstrated and confirmed by Transmission Electron Microscopy (TEM) and Raman measurements. The tensile stress can be reduced by up to 85%. Multiple iterations of implantation and annealing have been explored and can improve the stress relaxation.

Further studies will aim at improving the crystalline quality of the relaxed layers.

Principle of sSOI relaxation – © FAMES

 

TEM Cross-sections of a sSOI substrate after Si implantation (a) and post annealing (b) (thinner sample). After annealing a full recrystallization of the layer is observed – © FAMES

Scientific contact

Claire FENOUILLET-BERANGER, CEA-Leti 

Laurent Brunet, CEA-Leti

Philippe Rodriguez, CEA-Leti

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