VASCO : Silicon-ready solutions on for high-end security on FD-SOI technology
Through the Cyber Resilience Act and Chips Act, it is now mandatory to integrate hardware security solutions into every future electronic component, ensuring a resilient and secure digital future. While physical attacks pose a major threat to today’s digital product, security solutions have to be validated on ASICs rather than on FPGAs.
VASCO#64 is a groundbreaking effort designed to address the most prominent challenges in hardware security today by delivering silicon-ready security solutions on FD-SOI technology.
As the digital threat landscape expands at an unprecedented pace—fueled by AI and quantum advancements—the EU responds decisively. Through the Cyber Resilience Act and Chips Act, it is mandating the integration of hardware security solutions into every future electronic component, ensuring a resilient and secure digital future. Given the rising cyber threats targeting diverse markets—such as automotive, connectivity, IoT, and wearables— it is essential to extend cybersecurity standards across these sectors.
FPGA prototyping offers the flexibility and speed of functional validation but does not help for a rigorous security evaluation. While physical attacks, particularly fault injection and side-channel attacks, pose a major threat to today’s microcontrollers and more complex System on Chip (SoC), ASIC (Application-Specific Integrated Circuit) is then strictly required for the prototype and the evaluation of security primitive in the today’s challenge.
Within the frame of the FAMES pilot line and the willingness to extend the role of the FD-SOI technology among the semiconductor industry, VASCO#64 is a ground-breaking effort designed to address these challenges by delivering silicon-ready security solutions on FD-SOI technology. Driven by the ever more challenging standards in security such as Common Criteria, AIS31 or SESIP, VASCO#64 includes solutions to the most prominent challenges today in hardware security. Indeed, this solution aim at:
- Hardening application processor cores against physical attacks, such as fault injection and side-channel attacks,
- Developing secure implementations of quantum-ready cryptographic standards for Key Exchange Mechanisms (KEM), and
- Providing a reliable source of entropy on FD-SOI, paving the way for the first standard-ready True Random Number Generator (TRNG).
The VASCO#64 has been taped out in 2025 and is functional. The aforementioned IPs have been tested as functional and further characterization now aims at highlighting the expected security properties.
Illustrations:
Scientific contacts and contributors
Romain WACQUEZ, Mikael LE COADOU, Manuel PEZZIN, Mustapha EL MAJIHI, Florian PEBAY-PEYROULA, Licinius-Pompiliu BENEA, Gauthier ACHARD BACCATI, Stephano DI MATTEO, Emanuele VALEA, Simon PONTIÉ
Contact person for follow-up
Romain Wacquez, Mikaël Carmona, Florent Lepin, Manuel Pezzin.
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