Replacing the Past, Empowering the Future

With joint funding from the European Union and Business Finland, through the Chips JU FAMES pilot-line, VTT is now able to do large investments in semiconductor fabrication infrastructure. The new parameter analysers, replacing outdated legacy instruments from the 1980s-1990s, will empower our researchers to tackle ambitious goals, where more and better data will improve both the quality of analysis and the development time. Combined with our multiple automatic probe-stations, for up to 300 mm wafer size characterisation, we will have high throughput capability. This will enable continuous in-line fabrication monitoring inside the cleanroom, as well as extensive post-fabrication characterization in our measurement labs.

VTT Pilot-line Developments Tackling Global Challenges

In FAMES, VTT is developing two pilot-line platforms: bulk-acoustic-wave RF-filters and non-volatile-memories (NVMs). The NVM pilot-line will implement programmable semiconducting oxide FETs (SCO-FETs) that use scaled ferroelectric hafnium-zirconium-oxide (FE-HZO) to accomplish voltage-controlled switching. SCO is a promising group of materials that offer the potential of better performance, and higher scalability, as compared to Si-FETs. Furthermore, SCOs are BEOL compatible, meaning that they can be deposited in a low temperature process and integrated on top of Si-CMOS. A scanning electron microscopy (SEM) image of a VTT fabricated SCO-FET is shown in Figure 1a. At the 2025 IEEE Device Research Conference, VTT presented their method for optimizing the SCO-FET contact resistance.

In Figure 1b, a cross-sectional image made with transmission electron microscopy (TEM) of a VTT fabricated FE capacitor (FeCap) is shown. With electrical characterisation, we can demonstrate very uniform distributions of remanent polarization (P_r) across a 150 mm wafer, with distinct analogue states (data shown in Figure 1c). These results are part of a study recently submitted for publication.

SCO FeFETs integrated post-CMOS for analogue compute-in-memory could revolutionize AI computations, improving the efficiency >100x as compared to current state-of-the-art achieved with GPU accelerators, which rely on conventional von Neumann computing and volatile memories. These developments, with new materials, devices, and architectures, could potentially tackle the growing energy demand for AI that is posing a major global challenge going forward.