The 10nm FD-SOI Pathfinding PDK is a cornerstone of the open-access offer from the FAMES pilot line. As an exploratory technological design kit, it empowers users to evaluate the potential of the 10 nm FD-SOI node well before industrial maturity. This PDK aims to support the skills development of the European ecosystem (academics, SMEs, start-ups, industries) by providing early access to an advanced technology with high strategic value, while mitigating costs and risks associated with early-stage development.

The 10 nm FD-SOI Pathfinding PDK offers a comprehensive set of tools, rules, and models to design, simulate, and validate digital circuits on the 10 nm FD-SOI node in an exploratory framework.

The Design Rules Manual (DRM) describes all the layout rules tied to the technology. The values specified in this document are based on predictive data derived from technological projections. The DRM covers all Front-End-of-Line, Middle-of-Line and Back-End-of-Line (BEOL) modules, including a 68 nm contacted poly pitch, a 48 nm metal pitch, and a full BEOL stack with 10 metal levels.

Transistor models enable theoretical circuit performance evaluation, including leakage currents, variability, power consumption, and speed. These models encompass all thin oxide devices for super-low, low, regular and high threshold voltage options, with two poly bias choices (standard and low leakage). The models are compatible with the three simulators provided in the PDK: Eldo®, Spectre®, and HSPICE®.

Our solution includes all the necessary technological files and design environments for PDK utilization in standard Cadence EDA tools. The PDK features techfiles, simulation environments, symbols, and parametrised cells, allowing its complete integration into schematic and layout design flows.

Physical verification environments have also been set up. They include design-rule check flows, with over 1000 coded rules, as well as layout-versus-schematic flows, developed using Siemens Calibre® tools. This ensures consistency between schematic and layout within the FD-SOI 10 nm rules.

A parasitic extraction environment has been developed using StarRC® from Synopsys, and post-layout simulations have been integrated into Cadence Virtuoso ADE®. This enables realistic evaluation of circuit performances accounting for parasitic effects.

CEA-Leti, in collaboration CEZAMAT-WUT, has developed sixteen logic gate libraries, each comprising approximately 60 cells. The different logic gates correspond to combinations of the four threshold voltage levels, the two poly bias options, and two isolation schemes. This results in two series of libraries, one for high-density and another for high-performance circuits/applications. These libraries represent approximately 1,000 logic gates, forming an essential basis for exploring, characterizing, and evaluating the digital performance of the 10 nm FD-SOI node.

Finally, to enable comprehensive digital circuit evaluation, from Register Transfer Level description to final layout, we provide logic synthesis, placement and routing flows.