Relaxation of sSOI substrate for 10nm nMOS and pMOS FD-SOI devices co-integration
Introduction of strain is one of the main levers in order to achieve the performance for the new generation of 10nm FD-SOI devices. Tensile stress enhances the electron mobility for nMOS and hole mobility is improved by compressive stress for pMOS. In the case of sSOI (strain SOI) wafers, relaxing the tensile silicon for pMOS appears to be beneficial to facilitate the Ge condensation process (i.e., compressive strain). FAMES’ work published at the last EUROSOI-ULIS conference in April 2025, demonstrates 85% relaxation of a 1.25 GPa tensile sSOI wafer. Multiple iterations of ion implantation and annealing are also a promising solution and may be a path for further relaxation, making sSOI substrate essential for FD-SOI scaling.
Successful integration of PCM RF switches into 22 nm FD-SOI technology
CEA-Leti achieved the first integration of an RF switch based on a phase change material in the Back-end-of-line of a 300 mm FD-SOI technology at the 22 nm node. This breakthrough will enrich the FD-SOI CMOS technology offer with switches that outperform existing Radio-frequency switches in the terahertz frequency band. © FAMES Radio-frequency (RF) switches […]
BALI: Expanding the Horizons of 3D Integration
A new mask set dedicated to die-to-wafer (D2W) hybrid bonding and heterogeneous 3D integration has been developed to address the technological challenges of tomorrow. This mask set, named BALI, is the test vehicle of many current and future process developments involving 3D integration and including the pitch dimension downsizing and lower integration temperatures as targeted […]
