Design of Bulk Acoustic Wave Filters for the FR3 Range
Teams from VTT and CEA-Leti designed two Bulk Acoustic Wave Filters (BAW), aiming at respectively 8 and 15 GHz and near 500 MHz bandwidth, based on two complementary approaches. VTT designed its filter considering fundamental mode AlScN resonators, while CEA-Leti considered LiNbO3 resonators operating on their third resonance.
Advancements in 3D Sequential Integration for RF and Digital Co-Integration at mmWave Frequencies
A step forward in the maturity of 3D Sequential Integration (3DSI), where 5G (30GHz) RF circuits are stacked directly above a running digital circuit is demonstrated. It was shown that vertical digital/RF co-integration exhibits cross-talk only in specific conditions which may be properly handled by design and frequency plan definition despite the ultra-short proximity between tiers specific to 3DSI.
A 22FDX dual-mode wideband Radar receiver combining FM and Impulse Radar Waveform
A RADARCONF publication will detail early October’25 the receiver architecture implementing a dual-mode 3GHz-bandwidth Radar detection. The parallel scheme using digital code and analog integration together with 2 x 16 ADCs select the necessary bandwidth and operate using a sub-set of ADCs, reducing complexity and consumption in GF 22FDX.
CEA-Leti demonstrates first FeRAM NVM technology embedded in Global Foundries 22FDX platform
CEA-Leti research engineers have demonstrated for the first time a scalable Hf0.5Zr0.5O2 (HZO) based ferroelectric capacitor platform integrated into the back-end-of-line (BEOL) at the 22nm FD-SOI technology node. This breakthrough, reported at the IEDM 2024 conference, represents a major milestone in ferroelectric memory technology, significantly advancing scalability for embedded applications and positioning ferroelectric RAM (FeRAM) as a competitive memory solution for advanced nodes.
Relaxation of sSOI substrate for 10nm nMOS and pMOS FD-SOI devices co-integration
Introduction of strain is one of the main levers in order to achieve the performance for the new generation of 10nm FD-SOI devices. Tensile stress enhances the electron mobility for nMOS and hole mobility is improved by compressive stress for pMOS. In the case of sSOI (strain SOI) wafers, relaxing the tensile silicon for pMOS appears to be beneficial to facilitate the Ge condensation process (i.e., compressive strain). FAMES’ work published at the last EUROSOI-ULIS conference in April 2025, demonstrates 85% relaxation of a 1.25 GPa tensile sSOI wafer. Multiple iterations of ion implantation and annealing are also a promising solution and may be a path for further relaxation, making sSOI substrate essential for FD-SOI scaling.
Successful integration of PCM RF switches into 22 nm FD-SOI technology
CEA-Leti achieved the first integration of an RF switch based on a phase change material in the Back-end-of-line of a 300 mm FD-SOI technology at the 22 nm node. This breakthrough will enrich the FD-SOI CMOS technology offer with switches that outperform existing Radio-frequency switches in the terahertz frequency band. © FAMES Radio-frequency (RF) switches […]
BALI: Expanding the Horizons of 3D Integration
A new mask set dedicated to die-to-wafer (D2W) hybrid bonding and heterogeneous 3D integration has been developed to address the technological challenges of tomorrow. This mask set, named BALI, is the test vehicle of many current and future process developments involving 3D integration and including the pitch dimension downsizing and lower integration temperatures as targeted […]
