VASCO : Silicon-ready solutions on for high-end security on FD-SOI technology
VASCO#64 is an ASIC that aims at prototyping and demonstrating solutions to the most prominent challenges today in hardware security
Contact Punch-Through Failure Mitigation for Advanced FD-SOI Nodes
The study explores the mitigation of contact punch-through failures in advanced FD-SOI nodes by introducing a thin SiCO layer beneath the contact etch stop layer. We demonstrate that this integration optimization significantly improves contact robustness and therefore relaxes contact placement constraints within the device active region, offering a cost-effective solution to alleviate interconnect congestion in advanced FD-SOI nodes.
Tyndall Demonstrates First-Ever Tether-Free Micro-Transfer Printing of Si-based Micro-Inductor chiplets
The Tyndall FAMES team demonstrates the first tether-free micro-transfer printing of silicon-based micro-inductors, enabling both on-glass and in-substrate integration for compact power delivery. This breakthrough, presented at ECTC 2026, opens a scalable route to embed magnetic passives directly into advanced packaging platforms and future PowerSoC.
How FD-SOI is 150 times more secure than bulk versus Laser Fault Injection
A publication at IEEE IOLTS conference in July 2026 has highlighted the strong advantage of the FD-SOI CMOS technologies as compared to the legacy bulk ones.
High-Bandwidth CMOS regulated cascode based transimpedance amplifier for short-range Optical communications
Designed in a 22 nm FD-SOI technology and operating from a 0.8 V supply, the Regulated Cascode (RGC) based TransImpedance Amplifier (TIA) achieves a transimpedance gain of 75.5 dBΩ and a −3 dB bandwidth of 4.3 GHz while driving a 150 fF GaN photodiode.
Hybrid hardware advances energy-efficient optimization
By coupling memristors and stochastic magnetic tunnel junctions, the prototype solves hard tasks and could enable compact, low-energy accelerators
Planar self-biased circulator design and simulation
Simulations by SAL show promising performance for planar self-biased circulators, that are much smaller than the existing solutions relying on permanent magnets. This is the first step towards full integration of RF devices on FD-SOI technology.
3D Integrated Power Conversion: Tyndall and CEA-Leti Bring DC-DC Conversion Inside Advanced Packages
A major milestone in advanced power delivery technologies with the tape-out of a Power Management Integrated Circuit (PMIC) in advanced FD-SOI technology.
Localised Strain Engineering for Next-Gen FD-SOI MOSFETs
CEA-Leti successfully demonstrates how targeted Xe, Ar, and Ge ion implantations can modulate the mechanical strain of the Contact Etch Stop Layer (CESL).
SADP implementation at the gate-level patterning for the 7nm FD-SOI node
These results demonstrate the feasibility of extending planar FD-SOI technology toward 7nm node using a low-cost gate patterning solution such as SADP.
