3D Integrated Power Conversion: Tyndall and CEA-Leti Bring DC-DC Conversion Inside Advanced Packages
A major milestone in advanced power delivery technologies with the tape-out of a Power Management Integrated Circuit (PMIC) in advanced FD-SOI technology.
Localised Strain Engineering for Next-Gen FD-SOI MOSFETs
CEA-Leti successfully demonstrates how targeted Xe, Ar, and Ge ion implantations can modulate the mechanical strain of the Contact Etch Stop Layer (CESL).
SADP implementation at the gate-level patterning for the 7nm FD-SOI node
These results demonstrate the feasibility of extending planar FD-SOI technology toward 7nm node using a low-cost gate patterning solution such as SADP.
Ferroelectric HfO2/ZrO2 Superlattice Capacitors with High Center to Edge Wafer-Scale Uniformity
Ferroelectric HfO₂/ZrO₂ superlattice capacitors were fabricated with high wafer-scale uniformity by reducing the impact of process variations.
Impact of Device Position within the Silicon Active Area on Self-Heating and Thermal Coupling in FDSOI Transistors
UCLouvain and CEA-Leti analyzed how the transistor position within the silicon active area affects self-heating and thermal coupling in FDSOI Technology.
Release of the first 10 nm FD-SOI technology Pathfinding PDK
The first Pathfinding Process Design-Kit (PDK) for the 10 nm FD-SOI technology node is now available. This PDK enables an early evaluation of the technology for digital applications.
“MagIC” at Tyndall: Making Magnetics Disappear into ICs using Stripline Inductors with Laminated CZT Magnetic Cores
Tyndall “MagIC” achieves a breakthrough in developing on-silicon stripline inductors using laminated Cobalt-Zirconium-Tantalum (CZT) cores, paving the way for ultra-compact power management.
Initial results on hardware security concept based on RRAM devices
Two recent publications in Solid-State Electronics from CEZAMAT WUT address RRAM technology applications. The studies combine experimental investigation and modeling to support reliable memory operation and hardware security applications, strengthening the technological foundations of emerging non-volatile memory solutions.
Si:P and SiGe:B Dual epitaxy development for 10nm FD-SOI Raised Source-Drain
Introduction of strain is one of the main levers in order to achieve the performance for the new generation of 10nm FD-SOI devices. Tensile stress enhances the electron mobility for nMOS and hole mobility is improved by compressive stress for pMOS.
Advancing 3D Integration in Europe: Leveraging PREVAIL Infrastructure for FAMES Technology Development
Thanks to key investments from the PREVAIL Test and Experimentation Facility (TEF), CEA-Leti has made significant progress in the procurement and installation of critical process tools to address the ultra-fine pitch interconnects and high density Through Silicon Vias (TSV) targeted in FAMES. CEA-Leti already highlights the start-up and partial qualification of the most strategic equipment for 3D activities in FAMES.
