Release of the first 10 nm FD-SOI technology Pathfinding PDK
The first Pathfinding Process Design-Kit (PDK) for the 10 nm FD-SOI technology node is now available. This PDK enables an early evaluation of the technology for digital applications.
“MagIC” at Tyndall: Making Magnetics Disappear into ICs using Stripline Inductors with Laminated CZT Magnetic Cores
Tyndall “MagIC” achieves a breakthrough in developing on-silicon stripline inductors using laminated Cobalt-Zirconium-Tantalum (CZT) cores, paving the way for ultra-compact power management.
Initial results on hardware security concept based on RRAM devices
Two recent publications in Solid-State Electronics from CEZAMAT WUT address RRAM technology applications. The studies combine experimental investigation and modeling to support reliable memory operation and hardware security applications, strengthening the technological foundations of emerging non-volatile memory solutions.
FAMES Pilot Line Inaugurated: Europe’s New Chip Innovation Hub
The FAMES Pilot Line was inaugurated at CEA in Grenoble, gathering European partners, industry and public authorities around the €830M initiative. Already operational, FAMES supports the development of next-generation semiconductor technologies across five key technologies, while providing open access to its pilot line to accelerate innovation and industrial transfer across Europe.
Si:P and SiGe:B Dual epitaxy development for 10nm FD-SOI Raised Source-Drain
Introduction of strain is one of the main levers in order to achieve the performance for the new generation of 10nm FD-SOI devices. Tensile stress enhances the electron mobility for nMOS and hole mobility is improved by compressive stress for pMOS.
Advancing 3D Integration in Europe: Leveraging PREVAIL Infrastructure for FAMES Technology Development
Thanks to key investments from the PREVAIL Test and Experimentation Facility (TEF), CEA-Leti has made significant progress in the procurement and installation of critical process tools to address the ultra-fine pitch interconnects and high density Through Silicon Vias (TSV) targeted in FAMES. CEA-Leti already highlights the start-up and partial qualification of the most strategic equipment for 3D activities in FAMES.
Design of Bulk Acoustic Wave Filters for the FR3 Range
Teams from VTT and CEA-Leti designed two Bulk Acoustic Wave Filters (BAW), aiming at respectively 8 and 15 GHz and near 500 MHz bandwidth, based on two complementary approaches. VTT designed its filter considering fundamental mode AlScN resonators, while CEA-Leti considered LiNbO3 resonators operating on their third resonance.
Advancements in 3D Sequential Integration for RF and Digital Co-Integration at mmWave Frequencies
A step forward in the maturity of 3D Sequential Integration (3DSI), where 5G (30GHz) RF circuits are stacked directly above a running digital circuit is demonstrated. It was shown that vertical digital/RF co-integration exhibits cross-talk only in specific conditions which may be properly handled by design and frequency plan definition despite the ultra-short proximity between tiers specific to 3DSI.
A 22FDX dual-mode wideband Radar receiver combining FM and Impulse Radar Waveform
A RADARCONF publication will detail early October’25 the receiver architecture implementing a dual-mode 3GHz-bandwidth Radar detection. The parallel scheme using digital code and analog integration together with 2 x 16 ADCs select the necessary bandwidth and operate using a sub-set of ADCs, reducing complexity and consumption in GF 22FDX.
CEA-Leti demonstrates first FeRAM NVM technology embedded in Global Foundries 22FDX platform
CEA-Leti research engineers have demonstrated for the first time a scalable Hf0.5Zr0.5O2 (HZO) based ferroelectric capacitor platform integrated into the back-end-of-line (BEOL) at the 22nm FD-SOI technology node. This breakthrough, reported at the IEDM 2024 conference, represents a major milestone in ferroelectric memory technology, significantly advancing scalability for embedded applications and positioning ferroelectric RAM (FeRAM) as a competitive memory solution for advanced nodes.
